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191 Open 684 Closed
191 Open 684 Closed
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Issues list

Vector Indexed Instructions' order is memory Consistency rule or just elements' order whose address overlap?
#1692 opened Oct 21, 2024 by AlexGJL
7
Consider changing the bit-order in a byte from right-to-left to left-to-right
#1691 opened Oct 18, 2024 by gintominto5329
7
how to understand the PMA and the PBMT?
#1687 opened Oct 17, 2024 by rock-ifly
2
How and when the RISC-V Virtual Memory plans to support DEP/SMEP/SMAP and Memory Encryption?
#1683 opened Oct 15, 2024 by Steven-Li-Xiaogang
1
Possibility of 'Environment call from S-mode' delegation to S-mode
#1673 opened Oct 4, 2024 by evgeniy-paltsev
1
"...will be furninshed by the forthcoming extension" comments need to be removed Good First Issue This label indicates an issue that is well suited for a new contributor to tackle.
#1672 opened Oct 4, 2024 by Timmmm
Vector CSRs missing from CSR listing table Good First Issue This label indicates an issue that is well suited for a new contributor to tackle.
#1671 opened Oct 4, 2024 by Timmmm
Remove J extension placeholder chapter
#1668 opened Oct 3, 2024 by wmat
1
Help wanted: WARL and WLRL definitions help wanted
#1655 opened Sep 26, 2024 by kersten1
question about vstart
#1641 opened Sep 19, 2024 by ddxoxpp
Add instruction names
#1638 opened Sep 16, 2024 by ThinkOpenly
3
Which of RV64GBCV, RV64GCBV, and RV64GCVB is legal?
#1628 opened Sep 5, 2024 by songdongsheng
1
Zcmt: clarify translation of jvt-based addresses in M-mode
#1609 opened Aug 22, 2024 by Wren6991
5
Formulas (images) not displayed in Apple Books v6.4
#1607 opened Aug 21, 2024 by kbroch-rivosinc
4
Enhance RISC-V Instruction Documentation
#1590 opened Aug 8, 2024 by AFOliveira
9
Manuals reference in the main ISA
#1571 opened Jul 29, 2024 by AlfredoRodrigues4
Standardize and automate instructions documentation
#1567 opened Jul 25, 2024 by AFOliveira
1
[Smrnmi] Handling delegated exception when mnstatus.NMIE=0
#1565 opened Jul 25, 2024 by shubham-333
2
Add Symbol Clarification
#1547 opened Jul 19, 2024 by AFOliveira
1
9
Will core 0 fence and then core 1 do fence.i make instruction fetch get the same instruction memory in a multicore system
#1544 opened Jul 18, 2024 by fanghuaqi
5
C.S{LL,RL,RA}I64 are never actually defined in prose
#1542 opened Jul 17, 2024 by nwf-msr
1
Preamble vs Revision History
#1535 opened Jul 15, 2024 by AlfredoRodrigues4
how to understand bit 63 in mstateen0 is defined to control access to the matching sstateen and hstateen CSRs?
#1528 opened Jul 13, 2024 by ZeyueShen
2
"RV32/64G instruction set listing" chapter should include _all_ the extensions
#1517 opened Jul 10, 2024 by enh-google
4
Request for clarification: Behaviour of PMU overflow interrupts when subset of counters assigned to guest
#1508 opened Jul 8, 2024 by punitagrawal
4
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